The present invention relates to pad invariant integrated circuits.
Integrated circuits (ICs) comprise complex circuit blocks, each circuit block further comprising a plurality of transistors. The transistors are normally constructed on a semiconductor substrate. Metal interconnects couple transistors. Pad structures are formed within the IC to couple the IC to external devices. A pad structure includes a metal pad to facilitate bonding of the IC in a printed-circuit-board (PCB). Within the IC, the metal pad couples to one or more circuits, typically input circuits or output circuits, to facilitate coupling of the external device to the IC. Thus a pad in a first IC couples to a pad in a second IC. Pad structures occupy a significant silicon area as each pad structure includes a metal pad, input or output buffers, electro-static-discharge (ESD) circuits, control circuits, clock circuits, registers, etc. Metal pads itself is very large to facilitate bonding. Thus the pad cost for a given plurality of ICs required in a reference system design is significant. Furthermore as pads couple between IC's, the I/O characteristics are extremely important to interface devices.
Traditionally, integrated circuit (IC) devices such as custom, semi-custom, or application specific integrated circuit (ASIC) devices have been used in electronic products to reduce cost, enhance performance or meet space constraints. However, the design and fabrication of custom or semi-custom ICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during manufacturing phase. Further, should bugs exist in the custom or semi-custom ICs, the design/fabrication cycle has to be repeated, further aggravating the time to market and engineering cost. As a result, ASICs serve only specific applications and are custom built for high volume and low cost applications.
Another type of semi custom device called a Gate Array customizes modular blocks at a reduced NRE cost by synthesizing the design using a software model similar to the ASIC. The missing silicon level design verification results in multiple spins and lengthy design iterations.
In recent years there has been a move away from custom or semi-custom ICs towards field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. Off the shelf, generic Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA) products greatly simplify the design cycle. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to optimize silicon performance. The flexibility of this programmability is expensive in terms of silicon real estate, but reduces design cycle and upfront NRE cost to the designer. Most FPGA solutions mandate an external memory (boot-ROM) to store configuration data, thus exacerbating the solution cost. The FPGA to memory interface is via high silicon consuming pad structures.
FPGAs offer the advantages of low non-recurring engineering costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late on in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the more traditional approaches. However, the conversion from an FPGA implementation to an ASIC implementation typically requires a complete redesign. Such redesign is undesirable in that the FPGA design effort is wasted. An ASIC does not require configuration data and does not interface with a boot-ROM.
Compared to PLD and FPGA, an ASIC has hard-wired logic connections, identified during the chip design phase, and need no configuration memory cells. This is a large chip area and cost saving for the ASIC. Smaller ASIC die sizes lead to better performance. A full custom ASIC also has customized logic functions which take less gate counts compared to PLD and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count PLD or FPGA. The trade-off is between time-to-market (PLD and FPGA advantage) versus low cost and better reliability (ASIC advantage).
There is no convenient migration path from a PLD or FPGA used as a design verification and prototyping vehicle to the lower die size ASIC. All of the SRAM or Anti-fuse configuration bits and programming circuitry has no value to the ASIC. Programmable module removal from the PLD or FPGA and the ensuing layout and design customization is time consuming with severe timing variations from the original design. The pad structures play a major role in FPGA I/O interface characteristics, and matching those in a design conversion is not a simple exercise.
FIG. 1A shows prior-art arrangement of a first IC 100 coupled to a second IC 101. The first IC 100 includes a first transistor layer 102 having one or more circuit blocks 104. IC 100 includes one or more metal pads 103, each pad coupled to a circuit block such as 104. Typically, metal pad 104 is located substantially above the transistor layer 102. When IC 100 is an FPGA, circuit blocks 104 include I/O blocks, programmable logic blocks, and configuration memory. Data at pad 103 is received by a first circuit block 104 interfacing the pad, and then programmed into memory elements within configuration circuits. Second IC 101 includes a second transistor layer 106 having one or more circuit blocks 108. Each metal pad 107 in IC 101 is coupled to a circuit block such as 108. When IC 101 is a memory device, circuit blocks 107 include I/O blocks, memory arrays, and sense amplifiers. Data received/transmitted at pad 107 is handled by a circuit block 108 interfacing the pad. Thus pads 103 and 107 form a bus structure for data transfer between devices. FIG. 2A shows a second embodiment of prior art device coupling. In FIG. 1B, pads 117 and 113 are first coupled to a common metal trace 120. Both ICs incur a large Si area for I/O's, and have limited pads to connect to each other.